Java Compilation for Multi-threaded Architectures

This paper outlines the design of a compilation framework for applications in embedded systems programmed in Java and targeted at multi-threaded architectures. These architec-tures have multiple Thread Processing Units (TPUs) to support loop-level parallelism, where each TPU employs instruction-level parallelism, and data and control speculation techniques to improve performance. The paper describes the compilation framework, with particular emphasis on the design of the Java Intermediate Representation (JIR) based on Static Single-Assignment (SSA). The framework cleanly separates target-independent compilation issues from target-speciic ones, which enables the comparative study of multi-threaded models of computation.